Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived.
From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design.
CN103138763B - 一种动态器件匹配方法及运用该方法的电路 - Google Patents
Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time.
Post-layout simulation results in a 0. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced.
CNB - 一种动态器件匹配方法及运用该方法的电路 - Google Patents
The maximum clock frequency of the proposed comparator can be increased to 2. The standard deviation of the input-referred offset is 7.
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- CN103138763B - 一种动态器件匹配方法及运用该方法的电路 - Google Patents.
Article :. Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters ADCs employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Since the offset voltages of the constituting sub-blocks of these converters pre-amplifiers, folding circuits and latched comparators present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized:.
Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate certain IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners.